Spin orbit torque-magnetic random access memories (SOT-MRAMs) have been proposed, which are magnetic memories operating on the principle that data “0” is switched to data “1,” or vice versa, by reversing the spin direction in a storage layer of a magnetic tunnel junction (MTJ) element using spin orbit torque.
As the memory capacity increases, the cost per one bit (bit cost) of memory cells is required to be reduced as much as possible. One option for reducing the bit cost is reducing the area of a one-bit cell.
Examples of physical layout for forming an MTJ selection transistor for selecting an MTJ element in an SOT-MRAM, which is a planar transistor, have been known. A planar transistor here means a transistor in which the channel (current path) extends along the surface of a semiconductor substrate. No layout example for forming an SO (Spin Orbit) layer selection transistor for selecting an SO layer, which is a conductive layer providing the spin orbit torque, has been disclosed.